CS42526 Datasheet, PDF (49/90 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42526
in the Receiver Mode Control (address 1Eh) register to set the appropriate sample rate.
DAC_DEM
reg03h[1]
0
1
1
FRC_PLL_LK
reg06h[0]
X
0
1
DE-EMPH[1:0]
reg1Eh[5:4]
XX
XX
00
01
10
11
Table 5. DAC De-Emphasis
De-Emphasis
Mode
No De-Emphasis
Auto-Detect Fs
Reserved
32 kHz
44.1 kHz
48 kHz
6.4.5
RECEIVER DE-EMPHASIS CONTROL (RCVR_DEM)
Default = 0
Function:
When enabled, de-emphasis will be automatically applied when emphasis is detected based on the
channel status bits. The appropriate digital filter will be selected to maintain the standard 15µs/50µs
digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. If
the FRC_PLL_LK bit is set to a ‘1’b, then the auto-detect sample rate feature is disabled. To apply
the correct de-emphasis filter, use the DE-EMPH bits in the Receiver Mode Control (address 1Eh)
register to set the appropriate sample rate.
RCVR_DEM
reg03h[0]
0
1
1
FRC_PLL_LK
reg06h[0]
X
0
1
DE-EMPH[1:0]
reg1Eh[5:4]
XX
XX
00
01
10
11
Table 6. Receiver De-Emphasis
De-Emphasis
Mode
No De-Emphasis
Auto-Detect Fs
Reserved
32 kHz
44.1 kHz
48 kHz
6.5 Interface Formats (address 04h)
7
DIF1
6
DIF0
5
ADC_OL1
4
ADC_OL0
3
DAC_OL1
2
DAC_OL0
1
SAI_RJ16
0
CODEC_RJ16
6.5.1 DIGITAL INTERFACE FORMAT (DIFX)
Default = 01
Function:
These bits select the digital interface format used for the CODEC Serial Port and Serial Audio Interface
Port when not in one_line mode. The required relationship between the Left/Right clock, serial clock and
serial data is defined by the Digital Interface Format and the options are detailed in Figures 11-12.
DS585PP5
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