CS42526 Datasheet, PDF(6/90 Page) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

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CS42526 Datasheet, PDF (6/90 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

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CS42526

LIST OF TABLES

Table 1. Common OMCK Clock Frequencies ............................................................................... 26

Table 2. Common PLL Output Clock Frequencies........................................................................ 26

Table 3. Slave Mode Clock Ratios ................................................................................................ 26

Table 4. Serial Audio Port Channel Allocations............................................................................. 27

Table 5. DAC De-Emphasis .......................................................................................................... 49

Table 6. Receiver De-Emphasis.................................................................................................... 49

Table 7. Digital Interface Formats ................................................................................................. 50

Table 8. ADC One-Line Mode ....................................................................................................... 50

Table 9. DAC One-Line Mode ....................................................................................................... 50

Table 10. RMCK Divider Settings.................................................................................................. 52

Table 11. OMCK Frequency Settings............................................................................................ 53

Table 12. Master Clock Source Select .......................................................................................... 53

Table 13. AES Format Detection................................................................................................... 54

Table 14. Receiver Clock Frequency Detection ............................................................................ 55

Table 15. Example Digital Volume Settings .................................................................................. 58

Table 16. ATAPI Decode............................................................................................................... 60

Table 17. Example ADC Input Gain Settings ................................................................................ 61

Table 18. TXP Output Selection.................................................................................................... 62

Table 19. Receiver Input Selection ............................................................................................... 63

Table 20. Auxiliary Data Width Selection ...................................................................................... 66

Table 21. PLL External Component Values .................................................................................. 80

Table 22. Revision History .......................................................................................................... 89

DS585PP5

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