CS42518 Datasheet, PDF (56/91 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

CS42518
6.9.3
SYSTEM CLOCK SELECTION (ACTIVE_CLK)
Default = x
0 - Output of PLL
1 - OMCK
Function:
This bit identifies the source of the internal system clock (MCLK).
6.9.4 RECEIVER CLOCK FREQUENCY (RCVR_CLKX)
Default = xxx
Function:
The CS42518 will auto-detect the ratio between the OMCK and the recovered clock from the PLL,
which is displayed in register 07h. Based on this ratio, the absolute frequency of the PLL clock can
be determined, and this information is displayed according to the following table. If the absolute fre-
quency of the PLL clock does not match one of the given frequencies, this register will display the
closest available value.
NOTE: These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.
RCVR_CLK2 RCVR_CLK1 RCVR_CLK0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Description
8.1920 MHz
11.2896 MHz
12.288 MHz
16.3840 MHz
22.5792 MHz
24.5760 MHz
45.1584 MHz
49.1520 MHz
Table 14. Receiver Clock Frequency Detection
6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only)
7
PCx-7
PDx-7
6
PCx-6
PDx-6
5
PCx-5
PDx-5
4
PCx-4
PDx-4
3
PCx-3
PDx-3
2
PCx-2
PDx-2
1
PCx-1
PDx-1
6.10.1 BURST PREAMBLE BITS (PCX & PDX)
Default = xxh
Function:
The PC and PD burst preamble bytes are loaded into these four registers.
0
PCx-0
PDx-0
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DS584PP5