CS42518 Datasheet, PDF (27/91 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

SCLK/LRCK Ratio
CS42518
Single Speed
Double Speed
32x, 48x, 64x, 128x 32x, 48x, 64x
Quad Speed
32x, 48x, 64x
Table 3. Slave Mode Clock Ratios
One Line Mode #1
128x
4.6 Digital Interfaces
4.6.1 Serial Audio Interface Signals
The CS42518 interfaces to an external Digital Audio Processor via two independent serial ports, the
CODEC serial port, CODEC_SP and the Serial Audio Interface serial port, SAI_SP. The digital output of
the internal ADCs can be configured to use either the CX_SDOUT pin or the SAI_SDOUT pin and the
corresponding serial port clocking signals. These configuration bits and the selection of Single, Double or
Quad-Speed mode for CODEC_SP and SAI_SP are found in register “Functional Mode (address 03h)”
on page 49.
The serial interface clocks, SAI_SCLK for SAI_SP and CX_SCLK for CODEC_SP, are used for transmit-
ting and receiving audio data. Either SAI_SCLK or CX_SCLK can be generated by the CS42518 (master
mode) or it can be input from an external source (slave mode). Master or Slave mode selection is made
using bits CODEC_SP M/S and SAI_SP M/S in register “Misc Control (address 05h)” on page 52.
The Left/Right clock (SAI_LRCK or CX_LRCK) is used to indicate left and right data frames and the start
of a new sample period. It may be an output of the CS42518 (master mode), or it may be generated by
an external source (slave mode). As described in later sections, particular modes of operation do allow
the sample rate, Fs, of the SAI_SP and the CODEC_SP to be different, but must be multiples of each
other.
The serial data interface format selection (left/right justified, I²S or one line mode) for the Serial Audio In-
terface serial port data out pin, SAI_SDOUT, the CODEC serial port data out pin, CX_SDOUT, and the
CODEC input pins, CX_SDIN1:4, is configured using the appropriate bits in the register “Interface For-
mats (address 04h)” on page 50. The serial audio data is presented in 2's complement binary form with
the MSB first in all formats.
CX_SDIN1, CX_SDIN2, CX_SDIN3 and CX_SDIN4 are the serial data input pins supplying the associat-
ed internal DAC. CX_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs
and, when configured for one-line mode, up to four additional ADC channels attached externally to the
signals ADCIN1 and ADCIN2 (typically two CS5361 stereo ADCs). When operated in One Line Mode,
6 channels of DAC data are input on CX_SDIN1, two additional DAC channels on CX_SDIN4, and 6 chan-
nels of ADC data are output on CX_SDOUT. Table 4 outlines the serial port channel allocations.
CX_SDIN1
CX_SDIN2
CX_SDIN3
Serial Inputs / Outputs
left channel DAC #1
right channel DAC #2
one line mode DAC channels 1,2,3,4,5,6
left channel DAC #3
right channel DAC #4
one line mode not used
left channel DAC #5
right channel DAC #6
one line mode not used
Table 4. Serial Audio Port Channel Allocations
DS584PP5
27