CS42518 Datasheet, PDF (18/91 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

CS42518
AD0/CS
10 _{Address Bit 0 (I}²_{C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I}²_{C mode; CS}
is the chip select signal in SPI mode.
INT
11 Interrupt (Output) - The CS42518 will generate an interrupt condition as per the Interrupt Mask register.
See “Interrupts” on page 40 for more details.
RST
12 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
AINR-
AINR+
13 Differential Right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
14 modulators via the AINR+/- pins.
AINL+
AINL-
15 Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
16 modulators via the AINL+/- pins.
VQ
17 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
FILT+
18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
REFGND
19 Reference Ground (Input) - Ground reference for the internal sampling circuits.
AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
AOUTA4 +,-
AOUTB4 +,-
36,37 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the
35,34 Analog Characteristics specification table.
32,33
31,30
28,29
27,26
22,23
21,20
VA
VARX
24 Analog Power (Input) - Positive power supply for the analog section.
41
AGND
25 Analog Ground (Input) - Ground reference. Should be connected to analog ground.
40
MUTEC
38 Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power-on con-
dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
LPFLT
39 PLL Loop Filter (Output) - An RC network should be connected between this pin and ground.
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
42 S/PDIF Receiver Input/ General Purpose Output (Input/Output) - Receiver inputs for S/PDIF encoded
43 data. The CS42518 has an internal 8:2 multiplexer to select the active receiver port, according to the
44 Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins,
45 ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
46 registers.
47
48
RXP0
49 S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data.
TXP
50 S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the
receiver inputs as indicated by the Receiver Mode Control 2 register.
VLS
53 Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.
SAI_SDOUT
54 Serial Audio Interface Serial Data Output (Output) - Output for two’s complement serial audio PCM
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-
nal and external ADCs.
RMCK
55 Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference
(OMCK, pin 59) or the PLL which is locked to the incoming S/PDIF stream or CX_LRCK.
18
DS584PP5