CS42518 Datasheet, PDF (47/91 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

CS42518
6. REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, In-
terrupt Status Register, and Q-Channel Subcode Bytes and C-bit or U-bit Data Buffer, which are read
only. See the following bit definition tables for bit assignment information. The default state of each bit
after a power-up sequence or reset is listed in each bit description.
6.1 Memory Address Pointer (MAP)
Not a register
7
INCR
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
6.1.1 INCREMENT(INCR)
Default = 1
Function:
Memory address pointer auto increment control
0 - MAP is not incremented automatically.
1 - Internal MAP is automatically incremented after each read or write.
6.1.2
MEMORY ADDRESS POINTER (MAPX)
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control
port.
6.2 Chip I.D. and Revision Register (address 01h) (Read Only)
7
Chip_ID3
6
Chip_ID2
5
Chip_ID1
4
CHIP_ID0
3
Rev_ID3
2
Rev_ID2
6.2.1 CHIP I.D. (CHIP_IDX)
Default = 1110
Function:
I.D. code for the CS42518. Permanently set to 1110.
6.2.2
CHIP REVISION (REV_IDX)
Default = 0100
Function:
CS42518 revision level.
Revision D is coded as 0100.
Revision C is coded as 0011.
1
Rev_ID1
0
Rev_ID0
DS584PP5
47