DAC8552 Datasheet, PDF (4/22 Pages) Burr-Brown (TI) – 16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

DAC8552
SLAS430 – JULY 2006
PIN CONFIGURATION
DGK PACKAGE
MSOP-8
(Top View)
V_DD 1
V_REF 2
V_OUTB 3
V_OUTA 4
DAC8552
8 GND
7 D_IN
6 SCLK
5 SYNC
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PIN DESCRIPTIONS
PIN NAME
FUNCTION
1 V_DD
Power supply input, 2.7V to 5.5V
2 V_REF
Reference voltage input
3 V_OUTB Analog output voltage from DAC B
4 V_OUTA Analog output voltage from DAC A
5 SYNC
Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred on the falling edges of SCLK. The action specified by the
8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken
HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by
the DAC8552). Schmitt-Trigger logic input.
6 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz at 5V. Schmitt-Trigger logic input.
7 D_IN
Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input.
Schmitt-Trigger logic input.
8 GND
Ground reference point for all circuitry on the part.
4
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