DAC8552 Datasheet, PDF (15/22 Pages) Burr-Brown (TI) – 16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

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DAC8552
SLAS430 – JULY 2006
DB23
0
DB11
D11
SCLK
12
24th
Falling
Edge
12
24th
Falling
Edge
SYNC
D_IN
Invalid Write − Sync Interrupt:
SYNC HIGH before 24th Falling Edge
DB23 DB22
DB0
Valid Write - Buffer/DAC Update:
SYNC HIGH after 24th Falling Edge
DB23 DB22
DB1 DB0
Figure 44. Interrupt and Valid SYNC Timing
0
LDB
LDA
X
Buffer Select
PD1
PD0
D15
D14
D13
D10
D9
D8
D7
D6
D5
D5
D3
D2
D1
Figure 45. DAC8552 Data Input Register Format
DB12
D12
DB0
D0
D23
Reserved
D22
Reserved
D21
D20
Load B Load A
(Always Write 0)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
D19
Don't
Care
X
X
X
X
X
X
X
X
X
X
X
Table 2. Control Matrix
D18
Buffer
Select
0 = A,
1=B
#
#
#
0
1
#
0
1
#
0
1
D17 D16 D15 D14 D13–D0
PD1
PD0 MSB MSB-1
MSB-2...
LSB
DESCRIPTION
0
0
See Table 3
0
0
See Table 3
See Table 3
0
0
See Table 3
See Table 3
0
0
See Table 3
See Table 3
Data
X
Data
X
X
Data
X
X
Data
X
X
WR Buffer # w/Data
WR Buffer # w/Power-down Command
WR Buffer # w/Data and Load DAC A
WR Buffer A w/Power-Down Command and LOAD DAC A
(DAC A Powered Down)
WR Buffer B w/Power-Down Command and LOAD DAC A
WR Buffer # w/Data and Load DAC B
WR Buffer A w/Power-Down Command and LOAD DAC B
WR Buffer B w/Power-Down Command and LOAD DAC B
(DAC B Powered Down)
WR Buffer # w/Data and Load DACs A and B
WR Buffer A w/Power-Down Command and Load DACs A and
B (DAC A Powered Down)
WR Buffer B w/Power-Down Command and Load DACs A and
B (DAC B Powered Down)
Table 3. Power-Down Commands
D17
D16
PD1
PD0
0
1
1
0
1
1
OUTPUT IMPEDANCE POWER DOWN COMMANDS
1kΩ
100kΩ
High Impedance
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