DAC8552 Datasheet, PDF (17/22 Pages) Burr-Brown (TI) – 16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

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MICROPROCESSOR INTERFACING
DAC8552
SLAS430 – JULY 2006
DAC8552 to 8051 INTERFACE
Figure 46 shows a serial interface between the
DAC8552 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8552, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data is to be transmitted to the DAC8552,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second and third write cycle is initiated to transmit
the remaining data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
the serial data in a format which presents the LSB
first, while the DAC8552 requires its data with the
MSB as the first bit received. The 8051 transmit
routine must therefore take this into account, and
mirror the data as needed
80C51/80L51⁽¹⁾
P3.3
TXD
RXD
(1)Additional pins omitted for clarity.
DAC8552 ⁽¹⁾
SYNC
SCLK
D_IN
Figure 46. DAC8552 to 80C51/80L51 Interface
DAC8552 to Microwire INTERFACE
Figure 47 shows an interface between the DAC8552
and any Microwire compatible device. Serial data is
shifted out on the falling edge of the serial clock and
is clocked into the DAC8552 on the rising edge of
the SK signal.
Microwire^TM
CS
SK
SO
DAC8552⁽¹⁾
SYNC
SCLK
D_IN
(1) Additional pins omitted for clarity.
Microwire is a registered trademark of National Semiconductor.
Figure 47. DAC8552 to Microwire Interface
DAC8552 to 68HC11 INTERFACE
Figure 48 shows a serial interface between the
DAC8552 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8552, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
68HC11⁽¹⁾
PC7
SCK
MOSI
(1)Additional pins omitted for clarity.
DAC8552 ⁽¹⁾
SYNC
SCLK
D_IN
Figure 48. DAC8552 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is 0 and its CPHA bit is 1. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data is being
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
MSB first.) In order to load data to the DAC8552,
PC7 is left LOW after the first eight bits are
transferred, then a second and third serial write
operation is performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
DAC8552 to TMS320 DSP INTERFACE
Figure 49 shows the connections between the
DAC8552 and a TMS320 digital signal processor. By
decoding the FSX signal, multiple DAC8552s can be
connected to a single serial port of the DSP.
TMS320 DSP
FSX
DX
CLKX
DAC8552
V_DD
SYNC
D_IN
SCLK
V_OUTA
V_OUTB
V_REF
GND
Positive Supply
0.1µF
10µF
Output A
Output B
0.1µF
Reference
1µF to 10µF ^Input
Figure 49. DAC8552 to TMS320 DSP
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