DAC8552 Datasheet, PDF (13/22 Pages) Burr-Brown (TI) – 16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

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THEORY OF OPERATION
DAC SECTION
The architecture of each channel of the DAC8552
consists of a resistor-string DAC followed by an
output buffer amplifier. Figure 41 shows a simplified
block diagram of the DAC architecture.
DAC Register
V_REF
50kΩ
62kΩ
REF (+)
Register String
REF (−)
50kΩ
V
OUT
V_REF
V_REF
2
R
R_DIVIDER
R
GND
Figure 41. DAC8552 Architecture
DAC8552
SLAS430 – JULY 2006
To Output
Amplifier
(2x Gain)
The input coding for each device is unipolar straight
binary, so the ideal output voltage is given by:
VOUTA, B + VREF
D
65536
(1)
where D = decimal equivalent of the binary code that
is loaded to the DAC register; it can range from 0 to
65535. V_OUTA,B refers to channel A or B.
RESISTOR STRING
The resistor string section is shown in Figure 42. It is
simply a divide-by-2 resistor followed by a string of
resistors, each of value R. The code loaded into the
DAC register determines at which node on the string
the voltage is tapped off. This voltage is then applied
to the output amplifier by closing one of the switches
connecting the string to the amplifier.
OUTPUT AMPLIFIER
Each output buffer amplifier is capable of generating
rail-to-rail voltages on its output which approaches
an output range of 0V to V_DD (gain and offset errors
must be taken into account). Each buffer is capable
of driving a load of 2kΩ in parallel with 1000pF to
GND. The source and sink capabilities of the output
amplifier can be seen in the typical characteristics.
SERIAL INTERFACE
The DAC8552 uses a 3-wire serial interface (SYNC,
SCLK, and D_IN), which is compatible with SPI™ and
QSP™, and Microwire™ interface standards, as well
as most DSPs. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
R
R
Figure 42. Resistor String
The write sequence begins by bringing the SYNC
line LOW. Data from the D_IN line is clocked into the
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 30MHz,
making the DAC8552 compatible with high speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked into the shift register and
the shift register is locked. Further clocking does not
change the shift register data. Once 24 bits are
locked into the shift register, the 8 MSBs are used as
control bits and the 16 LSBs are used as data. After
receiving the 24th falling clock edge, the DAC8552
decodes the 8 control bits and 16 data bits to
perform the required function, without waiting for a
SYNC rising edge. A new SPI sequence starts at the
next falling edge of SYNC. A rising edge of SYNC
before the 24-bit sequence is complete resets the
SPI interface; no data transfer occurs.
After the 24th falling edge of SCLK is received, the
SYNC line may be kept LOW or brought HIGH. In
either case, the minimum delay time from the 24th
falling SCLK edge to the next falling SYNC edge
must be met in order to properly begin the next
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