CS4201 Datasheet, PDF (23/68 Pages) Cirrus Logic – CrystalClear Audio Codec 97 with headphone Amplifier

CS4201
4.1 Reset Register (Index 00h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 SE4 SE3 SE2 SE1 SE0 0 ID8 ID7 0
0 ID4 0
0
0
0
SE[4:0]
Crystal 3D Stereo Enhancement. SE[4:0] = 00110, indicating this feature is present.
ID8
18-bit ADC Resolution. The ID8 bit is ‘set’, indicating this feature is present.
ID7
20-bit DAC resolution. The ID7 bit is ‘set’, indicating this feature is present.
ID4
Headphone Out. The ID4 bit is ‘set’, indicating this feature is present. The state of this bit de-
pends on the state of the HPCFG pin.
Default
h. The data in this register is read-only data.
Any write to this register causes a Register Reset of the audio control (Index 00h - 3Ah) and Cirrus Logic defined
(Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4201.
4.2 Analog Mixer Output Volume Registers (Index 02h - 04h)
D15 D14 D13 D12 D11 D10 D9 D8 D7
Mute 0 ML5 ML4 ML3 ML2 ML1 ML0 0
D6 D5 D4 D3 D2 D1 D0
0 MR5 MR4 MR3 MR2 MR1 MR0
Mute
Output Mute. Setting this bit mutes the LINE_OUT_L/R or HP_OUT_L/R output signals.
ML[5:0]
Output Volume Left. These bits control the left master output volume. Each step corresponds
to 1.5 dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenuation. Set-
ting the ML5 bit sets the left channel attenuation to -46.5 dB by forcing ML[4:0] to a ‘1’ state.
ML[5:0] will read back 011111 when ML5 has been ‘set’. See Table 2 for further details.
MR[5:0]
Output Volume Right. These bits control the right master output volume. Each step corre-
sponds to 1.5 dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenu-
ation. Setting the MR5 bit sets the right channel attenuation to -46.5 dB by forcing MR[4:0] to
a ‘1’ state. MR[5:0] will read back 011111 when MR5 has been ‘set’. See Table 2 for further
details.
Default
8000h. This value corresponds to 0 dB attenuation and Mute ‘set’.
If the HPCFG pin is left floating, register 02h controls the Master Output Volume and register 04h controls the Head-
phone Output Volume. If the HPCFG pin is tied ‘low’, register 02h controls the Headphone Volume and register 04h
is a read-only register and always returns 0000h when ‘read’.
Mx5..Mx0
Write
000000
000001
…
011111
100000
...
111111
Mx5..Mx0
Read
000000
000001
…
011111
011111
...
011111
Gain
Level
0 dB
-1.5 dB
...
-46.5 dB
-46.5 dB
...
-46.5 dB
Table 2. Analog Mixer Output Attenuation
DS483PP3
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