CS4201 Datasheet, PDF (10/68 Pages) Cirrus Logic – CrystalClear Audio Codec 97 with headphone Amplifier

CS4201
AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: T_ambient = 25° C,
AVdd = 5.0 V, DVdd = 3.3 V; C_L = 55 pF load.
Parameter
Symbol
RESET Timing
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
(XTL mode)
(OSC mode)
(PLL mode)
T_{rst_low}
T_rst2clk
1st SYNC active to CODEC READY ‘set’
Vdd stable to RESET# inactive
Clocks
T_sync2crd
T_vdd2rst#
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter (depends on XTL_IN source)
F_clk
T_{clk_period}
BIT_CLK high pulse width
BIT_CLK low pulse width
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Data Setup and Hold
T_{clk_high}
T_{clk_low}
F_sync
T_{sync_period}
T_{sync_high}
T_{sync_low}
Output propagation delay from rising edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input signal rise time
Input signal fall time
Output signal rise time
(Note 4)
Output signal fall time
(Note 4)
Misc. Timing Parameters
T_co
T_isetup
T_ihold
T_irise
T_ifall
T_orise
T_ofall
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4) Warm Reset
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (ATE test mode)
Rising edge of RESET# to Hi-Z delay
(Note 4)
(Note 4)
T_{s2_pdown}
T_{sync_pr4}
T_sync2clk
T_setup2rst
T_off
Min
1.0
-
-
-
-
100
-
-
-
36
36
-
-
-
-
8
10
0
2
2
2
2
-
1.0
162.8
15
-
Typ
-
4.0
4.0
2.5
62.5
-
12.288
81.4
-
40.7
40.7
48
20.8
1.3
19.5
10
-
-
-
-
4
4
0.285
-
285
-
-
Max
-
-
-
-
-
-
-
-
750
45
45
-
-
-
-
12
-
-
6
6
6
6
1.0
-
-
-
25
Unit
µs
µs
µs
ms
µs
µs
MHz
ns
ps
ns
ns
kHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
10
DS483PP3