CS4201 Datasheet, PDF (16/68 Pages) Cirrus Logic – CrystalClear Audio Codec 97 with headphone Amplifier

CS4201
3. AC-LINK FRAME DEFINITION
The AC-link is a bi-directional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots.
Slot 0 is a special reserved time slot containing
16-bits which are used for AC-link protocol infra-
structure. Slots 1 through 12 contain audio or con-
trol/status data. Both the serial data output and
input frames are defined from the controller per-
spective, not from the CS4201 perspective.
The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.
Figure 9 shows the position of each bit location
within the frame. The first bit position in a new se-
rial data frame is F0 and the last bit position in the
serial data frame is F255. When SYNC goes active
(high) and is sampled active by the CS4201 (on the
falling edge of BIT_CLK), both devices are syn-
chronized to a new serial data frame. The data on
the SDATA_OUT pin at this clock edge is the final
bit of the previous frame’s serial data. On the next
rising edge of BIT_CLK, the first bit of Slot 0 is
driven by the controller on the SDATA_OUT pin.
On the next falling edge of BIT_CLK, the CS4201
latches this data in as the first bit of the frame.
Tag Phase
SYNC
BIT_CLK
12.288 MHz
81.4 ns
20.8 µ s
(48 kHz)
Data Phase
Bit Frame Position: F255
SDATA_OUT 0
F0
Valid
Frame
F1
Slot 1
Valid
F2
Slot 2
Valid
F12
F13
Slot 12
Valid
0
F14
Codec
ID1
F15
Codec
ID0
F16
R/W
F35
F36
0 WD15
F56
F57
D19 D18
F76
D19
F96
F255
D19
0
Bit Frame Position:
SDATA_IN
F255
GPIO
INT
F0
Codec
Ready
F1
Slot 1
Valid
F2
Slot 2
Valid
F12
F13
F14 F15
F16
Slot 12
Valid
0
0
0
0
F35
F36
0 RD15
F56 F57
D19 D18
F76
D19
F96
D19
F255
GPIO
INT
Slot 0
Slot 1
Slot 2
Slot 3
Figure 9. AC-link Input and Output Framing
Slot 4
Slots 5-12
16
DS483PP3