DEMO-ATF-5X1M4E Datasheet, PDF (13/16 Pages) Broadcom Corporation. – Low Noise Enhancement Mode Pseudomorphic HEMT in a Miniature Leadless Package

The value of resistors R1 and R2 are
calculated with the following for‑
mulas
R1 = V_gs
(2)
I_BB
R2 = ^(V_ds ^{– V}_gs^{) R1} (3)
V_gs
Example Circuit
V_DD = 5 V
V_ds = 3V
I_ds = 60 mA
V_gs = 0.58 V
Choose I_BB to be at least 10X the
maximum expected gate leakage
current. I_BB was chosen to be 2 mA for
this example. Using equations (1), (2),
and (3) the resistors are calculated as
follows
R1 = 290Ω
R2 = 1210Ω
R3 = 32.3Ω
R1 and R2 provide a constant voltage
source at the base of a PNP transistor
at Q2. The constant voltage at the base
of Q2 is raised by 0.7 volts at the emit‑
ter. The constant emitter voltage plus
the regulated V_DD supply are present
across resistor R3. Constant voltage
across R3 provides a constant current
supply for the drain current. Resistors
R1 and R2 are used to set the desired
V_ds. The combined series value of these
resistors also sets the amount of extra
current consumed by the bias net‑
work. The equations that describe the
circuit’s operation are as follows.
V_E = V_ds + (I_ds • R4) (1)
R3 = V_DD – V_E
(2)
I_ds
V_B = V_E – V_BE
(3)

V_B = R1 V_DD (4)
R1 + R2
Active Bias
Active biasing provides a means of
keeping the quiescent bias point con‑
stant over temperature and constant
over lot to lot variations in device dc
performance. The advantage of the
active biasing of an enhancement
mode PHEMT versus a depletion
mode PHEMT is that a negative power
source is not required. The techniques
of active biasing an enhancement
mode device are very similar to
those used to bias a bipolar junction
transistor.
V_DD = I_BB (R1 + R2) (5)
Rearranging equation (4)
provides the following formula
R2 = R₁ (V_DD – V_B) (4A)
V_B
and rearranging equation (5)
provides the follow formula
R1 =
V_DD
(5A)
( ) IBB 1 + VDD – VB
V_B
An active bias scheme is shown in
Figure 2.
INPUT
C1
Q1
Zo
C4
OUTPUT
Zo
L1
L4
L2
L3
C2
R5
C5
R4
C3
R6
C7
C6
R7
R1
Q2
R2
Vdd
R3
Figure 2. Typical ATF-541M4 LNA with Active Biasing.
Example Circuit
V_DD = 5 V
V_ds = 3V
I_ds = 60 mA
R4 = 10Ω
V_BE = 0.7 V
Equation (1) calculates the required
voltage at the emitter of the PNP
transistor based on desired V_ds and I_ds
through resistor R4 to be 3.6V. Equa‑
tion (2) calculates the value of resistor
R3 which determines the drain current
I_ds. In the example R3=23.3Ω. Equation
(3) calculates the voltage required at
the junction of resistors R1 and R2.
This voltage plus the step-up of the
base emitter junction determines the
regulated V_ds. Equations (4) and (5) are
solved simultaneously to determine
the value of resistors R1 and R2. In the
example R1=1450Ω and R2 =1050Ω.
Resistor R7 is chosen to be 1 kΩ. This
resistor keeps a small amount of current
flowing through Q2 to help maintain
bias stability. R6 is chosen to be 10 KΩ.
This value of resistance is high enough
to limit Q1 gate current in the presence
of high RF drive levels as experienced
when Q1 is driven to the P1dB gain
compression point. C7 provides a low
frequency bypass to keep noise from
Q2 effecting the operation of Q1. C7 is
typically 0.1 µF.
Maximum Suggested Gate Current
The maximum suggested gate current
for the ATF-541M4 is 2 mA. Incorpo‑
rating resistor R5 in the passive bias
network or resistor R6 in the active
bias network safely limits gate cur‑
rent to 500 µA at P1dB drive levels. In
order to minimize component count
in the passive biased amplifier circuit,
the 3 resistor bias circuit consisting
of R1, R2, and R5 can be simplified
if desired. R5 can be removed if R1 is
replaced with a 4.7KΩ resistor and if
R2 is replaced with a 27KΩ resistor.
This combination should limit gate
current to a safe level.
PCB Layout
A suggested PCB pad print for
the miniature, Minipak 1412 pack‑
age used by the ATF-541M4 is shown
in Figure 3.
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