AZV99 Datasheet, PDF (9/15 Pages) Arizona Microtek, Inc – PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable

AZV99
LOGIC DIAGRAMS AND PINOUTS FOR
AZV99NA, AZV99NB, AZV99ND
Q
D
D
470
470
V_BB
EN
4mA
V_EE
Q_HG
Q_HG
AZV99NA
Q
D
470
V_BB/D
EN
4mA
V_EE
Q_HG
Q_HG
AZV99NB
AZV99ND
EN operation follows PECL functionality. See the
Timing Diagram.
MLP 8, 2x2mm
D1
AZV99NA
8Q
D2
V_BB 3
7 VCC
V_EE
6 ^QHG
EN 4
TOP VIEW
5 ^QHG
MLP 8, 2x2mm
D1
AZV99NB
8Q
V_BB/D 2
7 VCC
EN 3
6 ^QHG
V_{EE 4}
TOP VIEW
5 ^QHG
Bottom Center Pad is the V_EE
return.
MLP 8, 2x2mm
Q1
AZV99ND
8 V_CC
D2
7 QHG
V_BB/D 3
6 QHG
EN 4
TOP VIEW
5 V_EE
Bottom Center Pad may be left open
or tied to V_EE. Pin 5 is the V_EE return.
Bottom Center Pad may be left open
or tied to V_EE. Pin 4 is the V_EE return.
April 2007 * REV - 9
www.azmicrotek.com
9