AZV99 Datasheet, PDF (2/15 Pages) Arizona Microtek, Inc – PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable

AZV99
MLP 8, 2x2 mm Package, NA, NB & ND Options
The MLP 8 NA, NB and ND options of the AZV99 provide a PECL/ECL level enable input (¯E¯N¯). When the
¯E¯N¯ input is LOW, the Q¯ and Q_HG/Q¯ _HG outputs pass data from the inputs. When ¯E¯N¯ is HIGH, the Q¯ output
continues to pass data while the Q_HG output is forced high and the Q¯ _HG output is forced low.
Only the Q¯ output operates with a current source (4 mA) to V_EE. This is accomplished by internal bonding of
CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes
4mA on-chip current source).
The AZV99NB and AZV99ND versions operates with a single ended data input (D). The D¯ input is internally
bonded directly to the V_BB pin bypassing the 470Ω bias resistor.
TSSOP 8 Package (T), MLP 8 Package, (N)
The TSSOP 8 (T) and MLP 8 (N) versions of the AZV99 provide a CMOS/TTL level enable input (EN). When
the EN input is HIGH, the Q¯ and Q_HG/Q¯ _HG outputs pass data from the inputs. When EN is LOW, the Q¯ output
continues to pass data while the Q_HG output is forced high and the Q¯ _HG output is forced low.
Only the Q¯ output operates with a current source (4 mA) to V_EE. This is accomplished by internal bonding of
CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes
4mA on-chip current source).
The TSSOP 8 (T) and MLP 8 (N) AZV99 operates with a single ended data input (D). The D¯ input is internally
bonded directly to the V_BB pin bypassing the 470Ω bias resistor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
PIN DESCRIPTION
PIN
D/D¯
Q/Q¯
Q_HG/Q¯ _HG
V_BB
EN-SEL
EN/E¯N¯
CS-SEL
V_EE
V_CC
FUNCTION
Data Inputs
PECL Data Outputs
LVDS Data Outputs
Reference Voltage Output
Selects Enable Logic
Enable Input
Selects Q and Q¯ Current Source Magnitude
Negative Supply
Positive Supply
ENABLE TRUTH TABLE
4mA EA.
Q
Q
D
D
470
V_BB
EN/EN
CMOS/TTL
THRESHOLD
CS-SEL
Q_HG
Q_HG
V_EE
EN-SEL
EN-SEL
EN/¯E¯N¯
Q/Q¯ Q_HG Q¯ _HG
NC
PECL Low or NC
Data Data Data
NC
PECL High or V_CC
Data High Low
V_EE1
CMOS/TTL Low, V_EE or NC Data High Low
V_EE1
CMOS/TTL High or V_CC2
Data Data Data
1 _{EN-SEL connections must be less than 1Ω.}
2 _{An external ≤20kΩ pull-up resistor between EN and VCC ensures a}
High when the EN pin is not driven.
CURRENT SOURCE TRUTH TABLE
CS-SEL
Q
Q¯
NC
4mA typ. 4mA typ.
V_EE1
V_CC1
8mA typ.
0
8mA typ.
4mA typ.
1 _{CS-SEL connections must be less than 1Ω.}
April 2007 * REV - 9
www.azmicrotek.com
2