HCTL-2017 Datasheet, PDF (9/12 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Position Data Latch
Quadrature Decoder Output
The position data latch is a 16-bit latch which captures
the position counter output data on each rising clock
edge, except when its inputs are disabled by the inhibit
logic section during four-byte read operations. The
output data is passed to the bus interface section. When
active, a signal from the inhibit logic section prevents
new data from being captured by the latch, keeping
the data stable while successive reads are made through
the bus section. The latch is automatically re-enabled
at the end of these reads. The latch is cleared to 0
asynchronously by the RST signal.
The quadrature decoder output section consists of
count and up/down outputs derived from the 4x
decoder mode of the HCTL-2021/2017. When the
decoder has detected a count, a pulse, one-half clock
cycle long, will be output on the CNT_DCDR pin. This
output will occur during the clock cycle in which the
internal counter is updated. The U/D pin will be set to
the proper voltage level one clock cycle before the rising
edge of the CNT_DCDR pulse, and held one clock cycle
after the rising edge of the CNT_DCDR pulse. These
outputs are not affected by the inhibit logic.
Inhibit Logic
Cascade Output
The Inhibit Logic Section samples the OE and SEL signals
on the falling edge of the clock and, in response to
certain conditions (see Figure 10), inhibits the position
data latch. The RST signal asynchronously clears the
inhibit logic, enabling the latch.
Bus Interface
The bus interface section consists of a 16 to 8 line
multiplexer and an 8-bit, three-state output buffer. The
multiplexer allows independent access to the low and
high bytes of the position data latch. The SEL and OE
signals determine which byte is output and whether or
not the output bus is in the high-Z state.
The cascade output also consists of count and up/down
outputs. When the HCTL-2021/2017 internal counter
overflows or underflows, a pulse, one-half clock cycle
long, will be output on the CNT_CAS pin. This output will
occur during the clock cycle in which the internal
counter is updated. The U/D pin will be set to the proper
voltage level one clock cycle before the rising edge of
the CNT_CAS pulse, and held one clock cycle after the
rising edge of the CNT_CAS pulse. These outputs are not
affected by the inhibit logic.
Step
SEL
OE
1
L
L
2
H
L
3
X
H
CLK
Falling
Falling
Falling
Inhibit Signal
1
1
0
Action
Set inhibit; read high byte
Read low byte; starts reset
Complete inhibit logic reset
Figure 10. Two Bytes Read Sequence
Figure 11. Simplified Inhibit Logic
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