HCTL-2017 Datasheet, PDF (6/12 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Figure 4. Bus Control Timing
Figure 5. Decoder, Cascade Output Timing
Operation
A block diagram of the HCTL-20xx family is shown in
Figure 6. The operation of each major function is
described in the following sections.
Figure 6. Simplified Logic Diagram
6