HCTL-2017 Datasheet, PDF (5/12 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Switching Characteristics
Table 5. Switching Characteristics Max/Min specifications at VDD = 5.0 ? 5%, TA = -40 to +85 OC, CL = 40 pf
Symbol Description
1
t_CLK
2
t_CHH
3
t_CD
Clock Period
Pulse width, clock high
Delay time, rising edge of clock to valid, updated count information on D0-7
4
t_ODE
Delay time, OE fall to valid data
5
t_ODZ
6
t_SDV
Delay time, OE rise to Hi-Z state on D0-7
Delay time, SEL valid to stable, selected data byte
(delay to High Byte = delay to Low Byte)
7
t_CLH
Pulse width, clock low
8
t_SS
Setup time, SEL before clock fall
9
t_OS
Setup time, OEN before clock fall
10 t_SH
Hold time, SEL after clock fall
11 t_OH
Hold time, OE after clock fall
12
t_RST
Pulse width, RST low
13
t_UDD
Delay time, U/D valid after clock rise
14
t_CHD
Delay time, CNT_DCDR or CNT_CAS high after clock rise
15
t_CLD
Delay time, CNT_DCDR or CNT_CAS low after clock fall
Min. Max. Units
30
ns
15
ns
31 ns
29 ns
29 ns
29 ns
15
ns
12
ns
12
ns
0
ns
0
ns
10
ns
4 29 ns
4 31 ns
4 31 ns
Figure 1. Reset Waveform
Figure 2. Waveforms for Positive Clock Edge Related Delays
Figure 3. Tri-State Output Timing
5