HCTL-2017 Datasheet, PDF (7/12 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Digital Noise Filter
The digital noise filter section is responsible for rejecting
noise on the incoming quadrature signals. The input
section uses two techniques to implement improved
noise rejection. Schmitt-trigger inputs and a three-clock-
cycle delay filter combine to reject low level noise and
large, short duration noise spikes that typically occur in
motor system applications. Both common mode and
differential mode noise are rejected. The user benefits
from these techniques by improved integrity of the data
in the counter. False counts triggered by noise are
avoided.
Figure 7 shows the simplified schematic of the input
section. The signals are first passed through a Schmitt-
trigger buffer to address the problem of input signals
with slow rise times and low-level noise (approximately
< 1V). The cleaned up signals are then passed to a four-
bit delay filter. The signals on each channel are sampled
on rising clock edges. A time history of the signals is
stored in the four-bit shift register. Any change on the
input is tested for a stable level being present for three
consecutive rising clock edges. Therefore, the filtered
output waveforms can change only after an input level
has the same value for three consecutive rising clock
edges.
Refer to Figure 8, which shows the timing diagram. The
result of this circuitry is that short noise spikes between
rising clock edges are ignored and pulses shorter than
two clock periods are rejected.
CHA
CK
D
Q
D
Q
D
Q
D
Q
CHB
D
Q
D
Q
D
Q
D
Q
CK
Figure 7. Simplified Digital Noise Filter Logic
3 t _CLK
CLK
JQ
CK
K
CHA
filtered
JQ
CK
K
CHB
filtered
CHA
t_E
t_E
t_ES
t_ES
t_ES
t_ES
CHB
Noise Spike
CHA
filtered
t_E
t_E
CHB
filtered
CHI
filtered
Figure 8. Signal Propagation through Digital Noise Filter
7