HCPL-M600500 Datasheet, PDF (7/11 Pages) AVAGO TECHNOLOGIES LIMITED – Small Outline, 5 Lead, High CMR, High Speed, Logic Gate Optocouplers

Switching Specifications
Over recommended temperature (T_A = -40°C to 85°C), V_CC = 5 V, I_F = 7.5 mA unless otherwise specified.
Parameter
Symbol
Device
HCPL- Min. Typ.* Max. Unit
Test Conditions
Fig. Note
Propagation
t_PLH
Delay Time
to High
Output Level
20
48
75 ns T_A = 25°C
100
R_L = 350 Ω
C_L = 15 pF
6, 7 5
8
Propagation
t_PHL
Delay Time
to Low
Output Level
25
50
75
100
T_A = 25°C
6, 7 6
8
Propagation
t_PSK
40
10,
Delay Skew
11
Pulse Width
Distortion
|t_PHL - t_PLH|
3.5 35
9 10
Output Rise
t_rise
24
Time
10
(10%-90%)
Output Fall
t_fall
10
Time
10
(10%-90%)
Common
Mode Transient
Immunity at High
Output Level
|CM_H|
M600
M601
M611
10,000
5,000 10,000
10,000 15,000
V/μs V_CM = 10 V
V_CM = 50 V
V_CM = 1000 V
V_O(min) = 2 V
R_L = 350 Ω
I_F = 0 mA
T_A = 25°C
11 7, 9
Common
Mode Transient
Immunity at Low
Output Level
|CM_H|
M600
M601
M611
10,000
5,000 10,000
10,000 15,000
V_CM = 10 V
V_CM = 50 V
V_CM = 1000 V
V_O(max) = 0.8 V
R_L = 350 Ω
I_F = 7.5 mA
T_A = 25°C
11 8, 9
*All typicals at T_A = 25°C, V_CC = 5 V.
Notes:
1. Bypassing of the power supply line is required with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler. The total lead length be-
tween both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed
20 mA.
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V_RMS for 1 second (Leakage detec-
tion current limit, I_I-O ≤ 5 μA).
5. The t_PLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the
output pulse.
6. The t_PHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the
output pulse.
7. CM_H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V_OUT >
2.0 V ).
8. CM_L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V_OUT > 0.8
V).
9. For sinusoidal voltages, (|dV_CM|/dt)_max = Sf_CMV_CM(p-p).
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. t_PSK is equal to the worst case difference in t_PHL and/or t_PLH that will be seen between units at any given temperature within the worst case
operating condition range.
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