HCTL-1100 Datasheet, PDF (37/40 Pages) Agilent(Hewlett-Packard) – General Purpose Motion Control ICs

There are three different timing
configurations which can be used
to give the user greater flexibility
to interface the HCTL-1100 to
most microprocessors (see
Timing diagrams). They are
differentiated from one another
by the arrangement of the ALE
signal with respect to the CS
signal. The three timing
configurations are listed below.
1. ALE, CS non-overlapped
2. ALE, CS overlapped
3. ALE within CS
Any I/O operation starts by
asserting the ALE signal which
starts sampling the external bus
into an internal address latch.
Rising ALE or falling CS during
ALE stops the sampling into the
address latch.
CS low after rising ALE samples
the external bus into the data
latch. Rising CS stops the
sampling into the data latch, and
starts the internal synchronous
process.
In the case of a write, the data in
the data latch is written into the
addressed location. In the case of
a read, the addressed location is
written into an internal output
latch. OE low enables the internal
output latch onto the external
bus. The OE signal and the
internal output latch allow the I/O
port to be flexible and avoid bus
conflicts during read operations.
It is important that the host
microprocessor does not attempt
to perform too many I/O
operations in a single sample time
of the HCTL-1100. Each
I/O operation interrupts the
execution of the HCTL-1100’s
internal code for 1 clock cycle.
Although extra clock cycles have
been allotted in each sample time
for I/O operations, the number of
extra cycles is reduced as the
value programmed into the
Sample Timer register (R0FH) is
reduced.
Table 5 shows the maximum
number of I/O operations allowed
under the given conditions.
The number of external clock
cycles available for I/O operations
in any of the four control modes
can be increased by increasing
the value in the Sample Timer
register (R0FH).
For every unit increase in the
Sample Timer register (R0FH)
above the minimums shown in
Table 5 the user may perform 16
additional I/O operations per
sample time.
data written to the 8-bit Motor
Command port by the control
algorithms is the internally
computed 2’s-complement motor
command with an 80H offset
added. This allows direct
interfacing to a DAC. Figure 16
shows a typical DAC interface to
the HCTL-1100. An inexpensive
DAC, such as MC1408 or
equivalent, has its digital inputs
directly connected to the Motor
Command port. The DAC pro-
duces an output current which is
converted to a voltage by an
operational amplifier. R and R
O
G
control the analog offset and gain.
The circuit is easily adjusted for
+5 V to –5 V operation by first
writing 80H to R08H and
adjusting R for 0 V output. Then
O
FFH is written to R08H and R_G is
adjusted until the output is 5 V.
Note that 00H in R08H
corresponds to –5 V out.
Interfacing the HCTL-1100 to
Amplifiers and Motors
The Motor Command port is the
ideal interface to an 8-bit DAC,
configured for bipolar output. The
Figure 17 shows an example of
how to interface the HCTL-1100
to an H-bridge amplifier. An H-
bridge amplifier allows bipolar
motor operation with a unipolar
power supply.
Table 5. Maximum Number of I/O Allowed
Sample Timer
Register Value
07H (07D)
OFH (15D)
Operating Mode
Position Control or
Prop. Vel. Control
Position Control or
Prop. Vel. Control
Trapezoidal Prof.
or Integral
Vel. Control
Maximum Number
of I/O Operations
Allowed per Sample
5
133
6
37