HCTL-1100 Datasheet, PDF (23/40 Pages) Agilent(Hewlett-Packard) – General Purpose Motion Control ICs

Inhibit option. Figure 6 shows the
output of the PWM port when Bit
0 is set.
Actual Position Registers
Read, Clear: R12H,R13H,R14H
Preset : R15H,R16H,R17H
The Actual Position Register is
accessed by two sets of registers
in the HCTL-1100. When reading
the Actual Position from the
HCTL-1100, the host processor
will read Registers R12H(MSB),
R13H, and R14H(LSB). When
presetting the Actual Position
Register, the processor will write
to Registers R15H(MSB), R16H,
and R17H(LSB).
When reading the Actual Position
registers, the order should be
R14H, R13H, R12H. These
registers are latched, such that,
when reading Register R14H, all
three bytes will be latched so that
count data does not change while
reading three separate bytes.
When presetting the Actual
Position Register, write to R15H
and R16H first. When R17H is
written to, all three bytes are
simultaneously loaded into the
Actual Position Register.
Note that presetting the Actual
Position Registers is only allowed
while the HCTL-1100 is in INIT/
IDLE mode.
The Actual Position Registers can
be simultaneously cleared at any
time by writing any value to
R13H.
Digital Filter Registers
Zero (A) R20H
Pole (B) R21H
Gain (K) R22H
All control modes use some part
of the programmable digital filter
D(z) to compensate for closed
loop system stability. The com-
pensation D(z) has the form:

A
K  z – ––– 
 256 
D(z) = –––––––––––
[1]

B
4  z + ––– 
 256 
where:
z = the digital domain operator
K = digital filter gain (R22H)
A = digital filter zero (R20H)
B = digital filter pole (R21H)
The compensation is a first-order
lead filter which in combination
with the Sample Timer T (R0FH)
affects the dynamic step response
and stability of the control
system. The Sample Timer, T,
determines the rate at which the
control algorithm gets executed.
All parameters, A, B, K, and T, are
8-bit scalars that can be changed
by the user any time.
As shown in equations [2] and
[3], the digital filter uses
previously sampled data to
calculate D(z). This old internally
sampled data is cleared when the
Initialization/Idle mode is
executed.
In Position Control, Integral
Velocity Control, and Trapezoidal
Profile Control the digital filter is
implemented in the time domain
as shown below:
MC = (K/4)(X ) –
n
n
[(A/256)(K/4)(X_n–1) +
(B/256)(MC )]
[2]
n-1
where:
n = current sample time
n-1 = previous sample time
MC_n = Motor Command Output
at n
MC_n-1 = Motor Command
Output at n-1
X_n = (Command Position –
Actual Position) at n
X_n-1 = (Command Position –
Actual Position) at n-1
In Proportional Velocity control
the digital compensation filter is
implemented in the time domain
as:
MC_n = (K/4)(Y_n)
[3]
where:
Y_n = (Command Velocity –
Actual Velocity) at n
For more information on system
sampling times, bandwidth, and
stability, please consult Avago
Application Note 1032, Design of
the HCTL-1000’s Digital Filter
Parameters by the Combination
Method.
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