HCPL-316J Datasheet, PDF (33/33 Pages) AVAGO TECHNOLOGIES LIMITED – 2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback

System Considerations
Propagation Delay Difference (PDD)
The HCPL-316J includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 62) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between
the high and low voltage motor rails, a potentially cata-
strophic condi­tion that must be prevented.
To minimize dead time in a given design, the turn-on of
the HCPL-316J driving Q2 should be delayed (relative to
the turn-off of the HCPL-316J driving Q1) so that under
worst-case conditions, transistor Q1 has just turned off
when transistor Q2 turns on, as shown in Figure 80. The
amount of delay necessary to achieve this condition is
equal to the maxi­mum value of the propagation delay
difference specification, PDD_MAX, which is specified to
be 400 ns over the operating temperature range of ‑40°C
to 100°C.
Delaying the HCPL-316J turn-on signals by the maximum
propaga­tion delay difference ensures that the minimum
dead time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead time is
equivalent to the difference between the maximum and
minimum propagation delay difference specifications
as shown in Figure 81. The maximum dead time for the
HCPL-316J is 800 ns (= 400 ns - (-400 ns)) over an operat-
ing temperature range of -40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal tempera­tures and test
conditions since the optocouplers under consider­a­tion
are typically mounted in close proximity to each other
and are switching identical IGBTs.
0.1
5 V + µF
–
V_IN+
V_IN-
V_CC1
GND1
RESET
FAULT
V_LED1+
V_LED1-
V_E
V_LED2+
DESAT
V_CC2
V_C
V_OUT
V_EE
V_EE
I_E
0.1
µF
0.1 µF
30 V
0.1 µF
+
–
30 V
0.1
5 V + µF
–
V_IN+
V_IN-
V_CC1
GND1
RESET
FAULT
V_LED1+
V_LED1-
V_E
V_LED2+
DESAT
V_CC2
V_C
V_OUT
V_EE
V_EE
I_E
0.1
µF
0.1 µF
30 V
0.1 µF
+
–
30 V
Figure 80. Minimum LED Skew for Zero Dead Time.
Figure 81. Waveforms for Dead Time Calculation.
HCPL-316J fig 60
HCPL-316J fig 61
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes AV01-0579EN
AV02-0717EN - April 9, 2009