HCPL-800J Datasheet, PDF (2/18 Pages) AVAGO TECHNOLOGIES LIMITED – Under-Voltage Detection

Block Diagram
Tx -en ¹
2
Tx -in
V _CC1
7
GND1 ⁸
Status ⁵
Rx -out ⁶
Tx -PD -out Tx -LD -in
13
12
AGC
Control IC
Status
Detection
G _R2
Tx LED
Driver
Shield
G _T2
Tx
TIA
Tx -en
Detection
Over -Temp
Detection
V _CC2 UVD
Load
Detection
Line Driver
Control
Status Logic
Rx
TIA
Shield
Rx LED
Driver
Amp
Line IC
4
3
Rx -Amp -in Rx -PD -out
15 _{Tx -out}
14 _{V CC2}
16 _GND2
11 _{C ext}
9 _{R ref}
10
Rx -in
Package Pin Out
1 Tx -en
2 Tx -in
3 Rx -PD -out
4 Rx -Amp -in
5 Status
6 Rx -out
7 V CC1
8 GND1
GND2 16
Tx -out 15
V CC2 14
Tx -PD -out 13
Tx -LD -in 12
C ext 11
Rx -in 10
R ref 9
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
Tx-en
Tx-in
Rx-PD-out
Rx-Amp-in
Status
Rx-out
V_CC1
GND1
R_ref
Rx-in
C_ext
Tx-LD-in
Tx-PD-out
V_CC2
Tx-out
GND2
Description
Transmit Enable Input
Transmit Input Signal
Rx Photodetector Output
Receiver Output Amplifier Input
Signal indicating Line Condition
Receiving Signal Output
5 V Power Supply
VCC1 Power Supply Ground
Sets Line Driver biasing current, typically 24 kΩ
Receiving Signal Input from Powerline
External Capacitor
Tx Line Driver Input
Tx Photodetector Output
5 V Power Supply
Transmit Signal Output to Powerline
VCC2 Power Supply Ground
2