HCPL-800J Datasheet, PDF (13/18 Pages) AVAGO TECHNOLOGIES LIMITED – Under-Voltage Detection

Test Circuit Diagrams
Unless otherwise noted, all test circuits are at T_A = 25°C, V_CC1 = 5 V, V_CC2 = 5 V, sinusoidal waveform input, and signal
frequency f = 132 kHz.
VCC1
SCOPE
VCC1
100 nF
1 _Tx-en
2 _Tx-in
3 _Rx-PD-out
4 _Rx-Amp-in
5 _Status
6 _Rx-out
7 _VCC1
8 _GND1
HCPL-800J
GND1
Figure 19. Load detection test circuit
GND2
Tx-out
VCC2
Tx-PD-out
Tx-LD-in
Cext
Rx-in
Rref
16
15
2.5 Ù
14
1 µF _RL
GND2
VCC2
13
100 nF
100 µF
12 ^{100 nF}
11
VIN = 1.5 VPP _GND2
1 µF
10
100 nF
9
Rref 24 kÙ
GND2
GND1
SCOPE
VOUT
1 kÙ
100 nF
GND1
VCC1
100 nF
1 _Tx-en
2 _Tx-in
3 _Rx-PD-out
4 _Rx-Amp-in
5 _Status
6 _Rx-out
7 _VCC1
8 _GND1
HCPL-800J
GND2
Tx-out
VCC2
Tx-PD-out
Tx-LD-in
Cext
Rx-in
Rref
16
15
100 nF 100 µF
14
13
5V
12
11
1 µF
10
100 nF
9
Rref 24 kÙ
GND1
VIM = 10 VPP
Figure 20. Isolation mode rejection ratio test circuit
GND2
VIN = 0.5 VPP
100 nF 2 kÙ
PULSE GEN.
GND1
VPULSE = 5 V,
fPULSE ¼1 kHz
VCC1
100 nF
1 _Tx-en
2 _Tx-in
3 _Rx-PD-out
4 _Rx-Amp-in
5 _Status
6 _Rx-out
7 _VCC1
8 _GND1
HCPL-800J
GND2
Tx-out
VCC2
Tx-PD-out
Tx-LD-in
Cext
Rx-in
Rref
16
GND2
15
100 nF
100 µF
14
VCC2
13
VOUT
12
11
1 µF
10
100 nF
9
Rref 24 kÙ
GND1
GND2
Figure 21. Tx-PD-out enable/ disable time test circuit
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