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SAM9M10_14 Datasheet, PDF (924/1385 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU
In the Interleaved Mode, the channels 0 to 3 corresponding to the Touch Screen inputs are automatically activated
and the bits CH0 to CH3 are automatically set in the “TSADCC Channel Status Register”.
This mode allows periodic conversion of the remaining channels at high sampling rate and converted data
transferred in memory with the PDC while the touch screen conversions are performed at low rate. The PDC
transfers only analog channel data and touch screen data must be read in the “TSADCC Channel Data Register x
(x = 0..7)”.
The resolution can be configured for the channel 4 to 7 only, through the LOWRES bit. The resolution for the
conversion made on channels 0 to 3 is forced to 10 bits.
At each trigger, the sequence performed depends on a Trigger Counter, which is compared at the end to the
Touch Screen Frequency, as defined by the field TSFREQ in the register TSADCC_MR:
Touch Screen Frequency = Trigger Frequency / (2TSFREQ+1)
unless TSFREQ is programmed at 0 or 1. In such cases, the Touch Screen Frequency is one-sixth of the Trigger
Frequency.
As TSFREQ varies between 0 and 15, this results in the ADC channels being converted between 6 to 65536 less
often than the Touch Screen channels.
If the bit PRES in “TSADCC Mode Register” is disabled (measure only position), the sequences are as follow:
 For Trigger Counter at 0:
1. Close the switches on the inputs XP and XM during the Sample and Hold Time.
2. Convert Channel XM and store the result in TSADCC_CDR1.
3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding
TSADCC_CDRx and TSADCC_LCDR.
4. Set Trigger Counter to 1.
 For Trigger Counter at 1:
1. Close the switches on the inputs XP and XM during the Sample and Hold Time.
2. Convert Channel XP, subtract TSADCC_CDR1 from the result and store the subtraction result in
TSADCC_CDR0 (and also in TSADCC_LCDR if PDCEN is enabled).
3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding
TSADCC_CDRx and TSADCC_LCDR.
4. Set Trigger Counter to 2.
 For Trigger Counter at 2:
1. Close the switches on the inputs XP and XM during the Sample and Hold Time.
2. Convert Channel YP,, subtract TSADCC_CDR1 from the result and store the subtraction result in
TSADCC_CDR1 (and also in TSADCC_LCDR if PDCEN is enabled).
3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding
TSADCC_CDRx and TSADCC_LCDR.
4. Set Trigger Counter to 3.
 For Trigger Counter at 3:
1. Close the switches on the inputs YP and YM during the Sample and Hold Time.
2. Convert Channel YM and store the result in TSADCC_CDR3.
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SAM9M10 [DATASHEET]
Atmel-6355G-ATARM-SAM9M10-Datasheet_02-Sept-14