SAM9M10_14 Datasheet, PDF (160/1385 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

19.2.4 I/O Lines Description
Table 19-2. EBI I/O Lines Description
Name
Function
EBI
EBI_D0 - EBI_D31
Data Bus
EBI_A0 - EBI_A25
Address Bus
EBI_NWAIT
External Wait Signal
SMC
EBI_NCS0 - EBI_NCS5
Chip Select Lines
EBI_NWR0 - EBI_NWR3
Write Signals
EBI_NRD
Read Signal
EBI_NWE
Write Enable
EBI_NBS0 - EBI_NBS3
Byte Mask Signals
EBI for NAND Flash Support
EBI_NANDCS
NAND Flash Chip Select Line
EBI_NANDOE
NAND Flash Output Enable
EBI_NANDWE
NAND Flash Write Enable
DDR2/SDRAM Controller
EBI_SDCK, EBI_SDCK#
DDR2/SDRAM Differential Clock
EBI_SDCKE
DDR2/SDRAM Clock Enable
EBI_SDCS
DDR2/SDRAM Controller Chip Select Line
EBI_BA0 - EBI_BA1
Bank Select
EBI_SDWE
DDR2/SDRAM Write Enable
EBI_RAS - EBI_CAS
Row and Column Signal
EBI_SDA10
SDRAM Address 10 Line
Type
I/O
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use
at the moment.
Table 19-3 on page 160 details the connections between the two Memory Controllers and the EBI pins.
Table 19-3. EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins
SDRAM I/O Lines
EBI_NWR1/NBS1/CFIOR
NBS1
EBI_A0/NBS0
Not Supported
EBI_A1/NBS2/NWR2
Not Supported
EBI_A[11:2]
SDRAMC_A[9:0]
EBI_SDA10
SDRAMC_A10
EBI_A12
Not Supported
EBI_A[14:13]
SDRAMC_A[12:11]
EBI_A[25:15]
Not Supported
EBI_D[31:0]
D[31:0]
SMC I/O Lines
NWR1
SMC_A0
SMC_A1
SMC_A[11:2]
Not Supported
SMC_A12
SMC_A[14:13]
SMC_A[25:15]
D[31:0]
160
SAM9M10 [DATASHEET]
Atmel-6355G-ATARM-SAM9M10-Datasheet_02-Sept-14