ATA6616 Datasheet, PDF (91/308 Pages) ATMEL Corporation – Single-package High Performance, Low Power AVR 8-bit Microcontroller with LIN

Atmel ATA6616/ATA6617
4.10.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 4-25 shows a func-
tional description of one I/O-port pin, here generically called Pxn.
Figure 4-25. General Digital I/O⁽¹⁾
QD
DDxn
Q _CLR
RESET
PUD
WDx
RDx
1
Pxn
QD
PORTxn
0
SLEEP
Q _CLR
RESET
RRx
WPx
WRx
SYNCHRONIZER
DQ
LQ
DQ
PINxn
Q
RPx
clk _I/O
PUD: PULLUP DISABLE
SLEEP: SLEEP CONTROL
clk_I/O : I/O CLOCK
WDx: WRITE DDRx
RDx: READ DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
WPx: WRITE PINx REGISTER
4.10.2.1
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O,
SLEEP, and PUD are common to all ports.
Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Regis-
ter Description for I/O Ports” on page 109, the DDxn bits are accessed at the DDRx I/O
address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O
address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
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