ATA6616 Datasheet, PDF (170/308 Pages) ATMEL Corporation – Single-package High Performance, Low Power AVR 8-bit Microcontroller with LIN

• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable
SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is
low when idle. Refer to Figure 4-60 and Figure 4-61 for an example. The CPOL functionality is
summarized below:
Table 4-41. CPOL Functionality
CPOL
0
1
Leading Edge
Rising
Falling
Trailing Edge
Falling
Rising
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first)
or trailing (last) edge of SCK. Refer to Figure 4-60 and Figure 4-61 for an example. The CPOL
functionality is summarized below:
Table 4-42. CPHA Functionality
CPHA
0
1
Leading Edge
Sample
Setup
Trailing Edge
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0
have no effect on the Slave. The relationship between SCK and the clk_IO frequency f_clkio is
shown in the following table:
Table 4-43. Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
SCK Frequency
0
0
0
f_clkio/4
0
0
1
f_clkio/16
0
1
0
f_clkio/64
0
1
1
f_clkio/128
1
0
0
f_clkio/2
1
0
1
f_clkio/8
1
1
0
f_clkio/32
1
1
1
f_clkio/64
170 Atmel ATA6616/ATA6617
9132D–AUTO–12/10