ATA6616 Datasheet, PDF (206/308 Pages) ATMEL Corporation – Single-package High Performance, Low Power AVR 8-bit Microcontroller with LIN

4.16.6.3
• Bit 3 - LERR: Error Interrupt
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective
enable bit - LENERR - is set in LINENIR.
– 0 = No error,
– 1 = An error has occurred.
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also
resets all LINERR bits.
In UART mode, this bit is also cleared by reading LINDAT.
• Bit 2 - LIDOK: Identifier Interrupt
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
– 0 = No identifier,
– 1 = Slave task: Identifier present, master task: Tx Header complete.
The user clears this bit by writing 1, in order to reset this interrupt.
• Bit 1 - LTXOK: Transmit Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR.
– 0 = No Tx,
– 1 = Tx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
• Bit 0 - LRXOK: Receive Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR.
– 0 = No Rx
– 1 = Rx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
LIN Enable Interrupt Register - LINENIR
Bit
7
6
5
4
3
2
1
0
-
-
-
-
LENERR LENIDOK LENTXOK LENRXOK LINENIR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:4 - Reserved Bits
– These bits are reserved for future use. For compatibility with future devices, they
must be written to zero when LINENIR is written.
• Bit 3 - LENERR: Enable Error Interrupt
– 0 = Error interrupt masked,
– 1 = Error interrupt enabled.
206 Atmel ATA6616/ATA6617
9132D–AUTO–12/10