SAM9N12 Datasheet, PDF (906/1137 Pages) ATMEL Corporation – The ARM926EJ-S based SAM9CN12 features the frequently requested combination of user...

on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in
ADC_EMR register, the 4 most significant bits are carrying the channel number thus allowing an
easier post-processing in the DMA buffer or better checking the DMA buffer integrity.
As soon as touchscreen conversions are required, the pen detection function may help the post-
processing of the buffer. To get more details refer to Section 42.7.10.4 ”Pen Detection Status”.
42.7.10.1
Classical ADC Channels Only
When no touchscreen conversion is required (i.e. TSMODE = 0 in ADC_TSMR register), the
structure of data within the buffer is defined by the ADC_MR, ADC_CHSR, ADC_SEQR1,
ADC_SEQR2 registers.
If the user sequence is not used (i.e. USEQ is cleared in ADC_MR register) then only the value
of ADC_CHSR register defines the data structure. For each trigger event, enabled channels will
be consecutively stored in ADC_LCDR register and automatically transferred to the buffer.
When the user sequence is configured (i.e. USEQ is set in ADC_MR register) not only does
ADC_CHSR register modify the data structure of the buffer, but ADC_SEQR1, ADC_SEQR2
registers may modify the data structure of the buffer as well.
Figure 42-12. Buffer Structure when TSMODE = 0
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 1
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 0
trig.event1
DMA Buffer
5
Structure
6
ADC_CDR5
ADC_CDR6
DMA Transfer
trig.event1
Base Address (BA)
DMA Buffer
0
BA + 0x02
Structure
0
ADC_CDR5
ADC_CDR6
8
trig.event2
5
ADC_CDR8
ADC_CDR5
BA + 0x04
BA + 0x06
0
trig.event2
0
ADC_CDR8
ADC_CDR5
6
ADC_CDR6
BA + 0x08
0
ADC_CDR6
8
ADC_CDR8
BA + 0x0A
0
ADC_CDR8
trig.eventN
5
6
8
ADC_CDR5
ADC_CDR6
ADC_CDR8
trig.eventN
BA + [(N-1) * 6]
0
BA + [(N-1) * 6]+ 0x02
0
BA + [(N-1) * 6]+ 0x04
0
ADC_CDR5
ADC_CDR6
ADC_CDR8
42.7.10.2
TouchScreen Channels Only
When only touchscreen conversions are required (i.e. TSMODE differs from 0 in ADC_TSMR
register and ADC_CHSR equals 0), the structure of data within the buffer is defined by the
ADC_TSMR register.
When TSMODE = 1 or 3, each trigger event adds 2 half-words in the buffer (assuming TSAV =
0), first half-word being XPOS of ADC_XPOSR register then YPOS of ADC_YPOSR register. If
TSAV/TSFREQ differs from 0, the data structure remains unchanged. Not all trigger events add
data to the buffer.
906 SAM9N12/SAM9CN11/SAM9CN12
11063G–ATARM–09-Oct-12