SAM9N12 Datasheet, PDF (754/1137 Pages) ATMEL Corporation – The ARM926EJ-S based SAM9CN12 features the frequently requested combination of user...

Figure 39-25. Read Access Ordered by a MASTER
SADR does not match,
TWI answers with a NACK
SADR matches,
TWI answers with an ACK
ACK/NACK from the Master
TWD
TXRDY
NACK
SVACC
SVREAD
EOSVACC
S ADR R NA DATA NA P/S/Sr SADR R A DATA A
Write THR
A DATA NA S/Sr
Read RHR
SVREAD has to be taken into account only while SVACC is active
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
39.10.5.2
Write Operation
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the
TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 39-26 on page 754 describes the Write operation.
Figure 39-26. Write Access Ordered by a Master
SADR does not match,
TWI answers with a NACK
SADR matches,
TWI answers with an ACK
Read RHR
TWD
RXRDY
SVACC
SVREAD
EOSVACC
S ADR W NA DATA NA P/S/Sr SADR W A DATA A
A DATA NA S/Sr
SVREAD has to be taken into account only while SVACC is active
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
754 SAM9N12/SAM9CN11/SAM9CN12
11063G–ATARM–09-Oct-12