SAM9N12 Datasheet, PDF (459/1137 Pages) ATMEL Corporation – The ARM926EJ-S based SAM9CN12 features the frequently requested combination of user...

SAM9N12/SAM9CN11/SAM9CN12
Table 31-7. Interleaved Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[12:0]
Bk[1:0]
Column[9:0]
M0
Row[12:0]
Bk[1:0]
Column[10:0]
M0
Row[12:0]
Bk[1:0]
Column[11:0]
M0
Table 31-8. Interleaved Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[13:0]
Bk[1:0]
Column[8:0]
M0
Row[13:0]
Bk[1:0]
Column[9:0]
M0
Row[13:0]
Bk[1:0]
Column[10:0]
M0
31.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks
Table 31-9. Linear Mapping for SDRAM Configuration: 8K Rows, 1024 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[2:0]
Row[12:0]
Column[9:0]
M0
Table 31-10. Linear Mapping for SDRAM Configuration: 16K Rows, 1024 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[2:0]
Row[13:0]
Column[9:0]
M0
Table 31-11. Interleaved Mapping for SDRAM Configuration: 8K Rows, 1024 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[12:0]
Bk[2:0]
Column[9:0]
M0
Table 31-12. Interleaved Mapping for SDRAM Configuration: 16K Rows, 1024 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[12:0]
Bk[2:0]
Column[9:0]
M0
11063G–ATARM–09-Oct-12
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