SAM9N12 Datasheet, PDF (745/1137 Pages) ATMEL Corporation – The ARM926EJ-S based SAM9CN12 features the frequently requested combination of user...

SAM9N12/SAM9CN11/SAM9CN12
Figure 39-17. TWI Write Operation with Multiple Data Bytes with or without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0?
Yes
Load Transmit register
TWI_THR = Data to send
No
Set the internal address
TWI_IADR = address
TWI_THR = data to send
Yes
Read Status register
No
TXRDY = 1?
Yes
Data to send?
Write STOP Command
TWI_CR = STOP
Read Status register
Yes
No
TXCOMP = 1?
END
11063G–ATARM–09-Oct-12
745