ATMEGA32_14 Datasheet, PDF (82/346 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega32(L)
Timer/Counter
Register – TCNT0
Output Compare
Register – OCR0
Timer/Counter
Interrupt Mask
Register – TIMSK
2503Q–AVR–02/11
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 42. Clock Select Bit Description
CS02 CS01 CS00 Description
0
0
0
No clock source (Timer/Counter stopped).
0
0
1
clk_I/O/(No prescaling)
0
1
0
clk_I/O/8 (From prescaler)
0
1
1
clk_I/O/64 (From prescaler)
1
0
0
clk_I/O/256 (From prescaler)
1
0
1
clk_I/O/1024 (From prescaler)
1
1
0
External clock source on T0 pin. Clock on falling edge.
1
1
1
External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
TCNT0[7:0]
TCNT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR0[7:0]
OCR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC0 pin.
Bit
Read/Write
Initial Value
7
OCIE2
R/W
0
6
TOIE2
R/W
0
5
TICIE1
R/W
0
4
OCIE1A
R/W
0
3
OCIE1B
R/W
0
2
TOIE1
R/W
0
1
OCIE0
R/W
0
0
TOIE0
R/W
0
TIMSK
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a compare match in Timer/Counter0 occurs, that is, when the OCF0 bit is set in the Timer/Coun-
ter Interrupt Flag Register – TIFR.
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