ATMEGA32_14 Datasheet, PDF (57/346 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega32(L)
Table 24. Overriding Signals for Alternate Functions in PA3..PA0
Signal Name
PA3/ADC3
PA2/ADC2
PA1/ADC1
PUOE
0
0
0
PUOV
0
0
0
DDOE
0
0
0
DDOV
0
0
0
PVOE
0
0
0
PVOV
0
0
0
DIEOE
0
0
0
DIEOV
0
0
0
DI
–
–
–
AIO
ADC3 INPUT
ADC2 INPUT
ADC1 INPUT
PA0/ADC0
0
0
0
0
0
0
0
0
–
ADC0 INPUT
Alternate Functions of The Port B pins with alternate functions are shown in Table 25.
Port B
Table 25. Port B Pins Alternate Functions
Port Pin Alternate Functions
PB7
SCK (SPI Bus Serial Clock)
PB6
MISO (SPI Bus Master Input/Slave Output)
PB5
MOSI (SPI Bus Master Output/Slave Input)
PB4
SS (SPI Slave Select Input)
AIN1 (Analog Comparator Negative Input)
PB3
OC0 (Timer/Counter0 Output Compare Match Output)
AIN0 (Analog Comparator Positive Input)
PB2
INT2 (External Interrupt 2 Input)
PB1
T1 (Timer/Counter1 External Counter Input)
T0 (Timer/Counter0 External Counter Input)
PB0
XCK (USART External Clock Input/Output)
The alternate pin configuration is as follows:
• SCK – Port B, Bit 7
SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a Slave,
this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as
a Master, the data direction of this pin is controlled by DDB7. When the pin is forced by the SPI
to be an input, the pull-up can still be controlled by the PORTB7 bit.
• MISO – Port B, Bit 6
MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master,
this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as
a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced by the SPI to
be an input, the pull-up can still be controlled by the PORTB6 bit.
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