ATMEGA32_14 Datasheet, PDF (127/346 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega32(L)
Timer/Counter
Register – TCNT2
Output Compare
Register – OCR2
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table
54.
Table 54. Clock Select Bit Description
CS22
CS21
CS20 Description
0
0
0
No clock source (Timer/Counter stopped).
0
0
1
clk_T2S/(No prescaling)
0
1
0
clk_T2S/8 (From prescaler)
0
1
1
clk_T2S/32 (From prescaler)
1
0
0
clk_T2S/64 (From prescaler)
1
0
1
clk_T2S/128 (From prescaler)
1
1
0
clk_T2S/256 (From prescaler)
1
1
1
clk_T2S/1024 (From prescaler)
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
TCNT2[7:0]
TCNT2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2 Register.
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR2[7:0]
OCR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC2 pin.
2503Q–AVR–02/11
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