ATF280F_14 Datasheet, PDF (82/107 Pages) ATMEL Corporation – Rad-Hard Reprogrammable FPGA

CR16/CR23 – GCK enable
• 0 = GCK 0:7 always enabled
• 1 = GCK 0:7 disabled during configuration download.
Setting CR16:C23 allows the user to disable the input buffers driving the global clocks. The clock buffers are enabled
and disabled synchronously with the rising edge of the respective GCLK signal, and stop in a High (“1”) state. Setting
one of these bits disables the appropriate GCLK input buffer only and has no effect on the connection from the input
buffer to the FPGA array.
CR24/CR27 – FCK enable
• 0 = FCK 0:3 always enabled
• 1 = FCK 0:3 disabled during configuration download.
Setting CR24:C27 allows the user to disable the input buffers driving the fast clocks. The clock buffers are enabled and
disabled synchronously with the rising edge of the respective FCLK signal, and stop in a High (“1”) state. Setting one of
these bits disables the appropriate FCLK input buffer only and has no effect on the connection from the input buffer to
the FPGA array.
CR28 - Reserved
Caution: must be '0'
CR29 - Not used (ignored)
CR30 – Global Set/Reset
• 0 = Global set/reset normal
• 1 = Global set/reset active (Low) during configuration
CR30 allows the Global set/reset hold the core DFFs in set/reset during any configuration download. The Global
set/reset net is released at the end of configuration download on the rising edge of CON.
CR31 – IO tristate
• 0 = Disable I/O tri-state
• 1 = I/O tri-state during configuration
CR31 forces all user defined I/O pins to go tri-state during configuration download. tri-state is released at the end of
configuration download on the rising edge of CON.
ATF280F [DATASHEET]
7750E−AERO−05/12
82