ATF280F_14 Datasheet, PDF (100/107 Pages) ATMEL Corporation – Rad-Hard Reprogrammable FPGA

16.5
AC parameters
All the timings are given at the worst case corner.
• All input I/O characteristics measured from VIH of 50% of VCC at the pad (CMOS threshold) to the internal VIH of
50% of VCC.
• All output I/O characteristics are measured as the average of TPDLH and TPDHL to the pad VIH of 50% of VCC.
• Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of
VCC.
• Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
All the values provided here after are simulation values. They are not measured on production environment.
Table 16-5. Propagation Delay characteristics
Cell Function
IO
Input 3.3V
Input 3.3V
Input 3.3V
Input 3.3V
Output, 3.3V, slow
Output, 3.3V,
medium
Output, 3.3V, fast
Output, 3.3V, slow
Output, 3.3V,
medium
Output, 3.3V, fast
Parameter Path
Value Units Notes
tPD
pad -> q 3.6
ns
propagation delay from pad to q, no extra
delay
tPD
pad -> q 3.7
ns
propagation delay from pad to q, extra delay
1
tPD
pad -> q 4.1
ns
propagation delay from pad to q, extra delay
3
tPD
pad -> q 4.6
ns
propagation delay from pad to q, extra delay
5
tPD
a -> pad 7.1
ns
propagation delay from a to pad, 40 pF load
tPD
a -> pad 6.2
ns
propagation delay from a to pad, 40 pF load
tPD
a -> pad 6.0
ns
propagation delay from a to pad, 40 pF load
tPD
oe -> pad 8.2
ns
propagation delay from oe to pad, 40 pF load
tPD
oe -> pad 7.4
ns
propagation delay from oe to pad, 40 pF load
tPD
oe -> pad 7.1
ns
propagation delay from oe to pad, 40 pF load
Table 16-6. Clock – Set/Reset AC characteristics
Function
Parameter Path
Global Clocks and Set/Reset
GCK Input pad at
tPD
3.3V
FCK Input pad at
tPD
3.3V
pad -> clk
pad -> clk
Reset Input pad at
tPD
3.3V
pad -> sn | rn
Value Units Notes
9.5
ns
delay from GCKx global clock pad to flop on
the rising edge clock
8
ns
delay from FCKx fast clock pad to flop on the
rising edge clock.
Warning: Flops must be placed on first or
last column of the matrix
10
ns
delay from any pad to the set/reset flop pin
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