ATF280F_14 Datasheet, PDF (12/107 Pages) ATMEL Corporation – Rad-Hard Reprogrammable FPGA

The following figure depicts the ATF280F cell which is a highly configurable logic block based around two 3-input LUTs
(8 x 1 ROM), and which can be combined to produce one 4-input LUT. This means that any cell can implement two
functions of 3 inputs or one function of 4 inputs.
Figure 3-3. ATF280F Core Cell
Every cell includes a register element, a D-type flip-flop, with programmable clock and reset polarities. The initialization
of the register is also programmable. It can be either SET or RESET. The flip-flop can be used to register the output of
one of the LUT. It can also be exploited in conjunction with the feedback path element to implement a complete ripple
counter stage in a single cell. The registered or unregistered output of each LUT can be feedback within the cell and
treated as another input. This allows, for example, a single counter stage to be implemented within one cell without
using external routing resources for the feedback connection.
There is also a 2-to-1 multiplexer in every cell, and an upstream AND gate in the “front end” of the cell. This AND gate is
an important feature in the implementation of efficient array multipliers as the product and carry terms can both be
generated within a single logic cell.
The cell flexibility makes the ATF280F architecture well suited for most of the digital design application areas.
ATF280F [DATASHEET]
7750E−AERO−05/12
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