ATF280F_14 Datasheet, PDF (42/107 Pages) ATMEL Corporation – Rad-Hard Reprogrammable FPGA

• CCLK: this signal is internally pulled-up,
• IO713_D0: this signal takes the value ouput by the EEPROM (first bit of the EEPROM),
• CON: this signal is driven to a low logic level,
• IO303_INIT: this signal is internally pulled-up,
• IO259_LDC: the Low During Configuration is driven to a low logic level,
• IO265_HDC: the High During Configuration is driven to a high logic level,
• RESETN: this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase.
[Idle]: During the Idle lifephase, the ATF280F continues releases the configuration download interface, this lifephase
starts when CON and IO303_INIT pins are released:
• M0, M1, M2: these signals remain inputs and are not used anymore,
• CCLK: this signal is internally pulled-up,
• IO713_D0: this signal takes its GPIO function and is internally pulled-up,
• CON: this signal is released to a high logic level,
• IO303_INIT: this signal takes its GPIO function and is internally pulled-up. Refer to Data Link Protection
section for serial configuration,
• IO259_LDC: this signal takes its GPIO function and is internally pulled-up,
• IO265_HDC: this signal takes its GPIO function and is internally pulled-up,
• IO547_CS0: this signal takes its GPIO function and is internally pulled-up,
• RESETN: this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase.
ATF280F [DATASHEET]
7750E−AERO−05/12
42