ATTINY20_13 Datasheet, PDF (81/220 Pages) ATMEL Corporation – 8-bit AVR Microcntroller with 2K Bytes In-System Programmable Flash

Figure 12-4. Output Compare Unit, Block Diagram
DATA BUS (8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit)
OCRnx Buffer (16-bit Register)
TCNTnH (8-bit)
TCNTnL (8-bit)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
TOP
BOTTOM
= (16-bit Comparator )
OCFnx (Int.Req.)
Waveform Generator
OCnx
WGMn[3:0] COMnx[1:0]
Figure 12-4 on page 81 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names
indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements
of the block diagram that are not directly a part of the Output Compare unit are gray shaded.
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the
Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-
free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU
has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does
not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit
registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done
continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the
TEMP Register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same
system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 93.
12.6.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the
Force Output Compare (1x) bit. Forcing compare match will not set the OCF1x flag or reload/clear the timer, but the
ATtiny20 [DATASHEET] 81
8235E–AVR–03/2013