ATTINY20_13 Datasheet, PDF (140/220 Pages) ATMEL Corporation – 8-bit AVR Microcntroller with 2K Bytes In-System Programmable Flash

Figure 17-9. TWI Arbitration
Figure 17-9 shows an example where two TWI masters are contending for bus ownership. Both devices are able to issue
a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2 is
transmitting a low level.
Arbitration between a repeated START condition and a data bit, a STOP condition and a data bit, or a repeated START
condition and STOP condition are not allowed and will require special handling by software.
17.3.9 Synchronization
A clock synchronization algorithm is necessary for solving situations where more than one master is trying to control the
SCL line at the same time. The algorithm is based on the same principles used for clock stretching previously described.
Figure 17-10 shows an example where two masters are competing for the control over the bus clock. The SCL line is the
wired-AND result of the two masters clock outputs.
Figure 17-10.Clock Synchronization
A high to low transition on the SCL line will force the line low for all masters on the bus and they start timing their low
clock period. The timing length of the low clock period can vary between the masters. When a master (DEVICE1 in this
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
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