ATTINY20_13 Datasheet, PDF (115/220 Pages) ATMEL Corporation – 8-bit AVR Microcntroller with 2K Bytes In-System Programmable Flash

Table 15-1. ADC Conversion Time
Condition
First conversion
Normal conversions
Auto Triggered conversions
Free Running conversion
Sample & Hold (Cycles from Start of Conversion)
13.5
1.5
2
2.5
Conversion Time (Cycles)
25
13
13.5
14
15.6
Changing Channel or Reference Selection
The MUX and REFS bits in the ADMUX Register are single buffered through a temporary register to which the CPU has
random access. This ensures that the channels and reference selection only takes place at a safe point during the
conversion. The channel and reference selection is continuously updated until a conversion is started. Once the
conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set).
Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not
to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when
updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed
in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely
updated in the following ways:
 When ADATE or ADEN is cleared.
 During conversion, minimum one ADC clock cycle after the trigger event.
 After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
15.6.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is
selected:
 In Single Conversion mode, always select the channel before starting the conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the
conversion to complete before changing the channel selection.
 In Free Running mode, always select the channel before starting the first conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first
conversion to complete, and then change the channel selection. Since the next conversion has already started
automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the
new channel selection.
15.6.2 ADC Voltage Reference
The ADC reference voltage (V_REF) indicates the conversion range for the ADC. Single ended channels that exceed V_REF
will result in codes close to 0x3FF. V_REF can be selected as either V_CC, or internal 1.1V reference. The internal 1.1V
reference is generated from the internal bandgap reference (V_BG) through an internal amplifier.
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
115