ATTINY20_13 Datasheet, PDF (102/220 Pages) ATMEL Corporation – 8-bit AVR Microcntroller with 2K Bytes In-System Programmable Flash

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 36) is
executed when the TOV1 flag, located in TIFR, is set.
12.11.9 TIFR – Timer/Counter Interrupt Flag Register
Bit
0x25
Read/Write
Initial Value
7
ICF1
R/W
0
6
5
4
3
2
1
0
–
OCF1B
OCF1A
TOV1
OCF0B
OCF0A
TOV0
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
TIFR
 Bit 7 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the
WGM1[3:0] to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by
writing a logic one to its bit location.
 Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B
(OCR1B).
Note that a Forced Output Compare (1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B
can be cleared by writing a logic one to its bit location.
 Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A
(OCR1A).
Note that a Forced Output Compare (1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A
can be cleared by writing a logic one to its bit location.
 Bit 3 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM1[3:0] bits setting. In Normal and CTC modes, the TOV1 flag is set when
the timer overflows. See Table 12-5 on page 98 for the TOV1 flag behavior when using another WGM1[3:0] bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can
be cleared by writing a logic one to its bit location.
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
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