ATXMEGA384C3_14 Datasheet, PDF (77/125 Pages) ATMEL Corporation – 8/16-bit Atmel XMEGA C3 Microcontroller

35.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 35-23. Internal PLL Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max. Units
f_IN
Input frequency
Output frequency must be within f_OUT
0.4
64
f_OUT
Output frequency ⁽¹⁾
V_CC= 1.6 - 1.8V
V_CC= 2.7 - 3.6V
20
48
MHz
20
128
Start-up time
Re-lock time
25
µs
25
Note:
1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
35.13.6 External Clock Characteristics
Figure 35-3. External Clock Drive Waveform
t_CH
t_CH
t_CR
t_CF
V_IH1
V_IL1
t_CL
t_CK
Table 35-24. External Clock⁽¹⁾
Symbol Parameter
Condition
Min.
Typ.
Max. Units
1/t_CK
Clock frequency⁽²⁾
V_CC = 1.6 - 1.8V
V_CC = 2.7 - 3.6V
0
90
MHz
0
142
t_CK
Clock period
V_CC = 1.6 - 1.8V
V_CC = 2.7 - 3.6V
11
7.0
ns
t_CH/CL Clock high/low time
V_CC = 1.6 - 1.8V
V_CC = 2.7 - 3.6V
4.5
2.4
V_IL/IH Low/high level input voltage
See Table on page 70
V
t_CK
Reduction in period time from one
clock cycle to the next
10
%
Notes:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
XMEGA C3 [DATASHEET]
77
Atmel-8361F-AVR-ATxmega384C3-Datasheet–11/2014