ATXMEGA384C3_14 Datasheet, PDF (61/125 Pages) ATMEL Corporation – 8/16-bit Atmel XMEGA C3 Microcontroller

Mnemonics
SPM
IN
OUT
PUSH
POP
XCH
LAS
LAC
LAT
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Operands
Z+
Rd, A
A, Rr
Rr
Rd
Z, Rd
Z, Rd
Z, Rd
Z, Rd
Rd
Rd
Rd
Rd
Rd
Rd
s
s
A, b
A, b
Rr, b
Rd, b
Description
Operation
Store Program Memory and Post-Increment by 2
(RAMPZ:Z)  R1:R0,
Z  ^Z+2
In From I/O Location
Rd  I/O(A)
Out To I/O Location
I/O(A)  Rr
Push Register on Stack
STACK  Rr
Pop Register from Stack
Rd  STACK
Exchange RAM location
Temp  _Rd,
Rd  (Z),
(Z) ^{ Temp}
Load and Set RAM location
Temp  _Rd,
Rd  (Z),
(Z) ^{ Temp v (Z)}
Load and Clear RAM location
Temp  _Rd,
Rd  (Z),
(Z) ^{ ($FFh – Rd)  (Z)}
Load and Toggle RAM location
Temp  _Rd,
Rd  (Z),
(Z) ^{ Temp  (Z)}
Bit and bit-test instructions
Logical Shift Left
Rd(n+1)  _Rd(n),
Rd(0)  0,
C ^{ Rd(7)}
Logical Shift Right
Rd(n)  _Rd(n+1),
Rd(7)  0,
C ^{ Rd(0)}
Rotate Left Through Carry
Rd(0)  _C,
Rd(n+1)  Rd(n),
C ^{ Rd(7)}
Rotate Right Through Carry
Rd(7)  _C,
Rd(n)  Rd(n+1),
C ^{ Rd(0)}
Arithmetic Shift Right
Rd(n)  Rd(n+1), n=0..6
Swap Nibbles
Rd(3..0)  Rd(7..4)
Flag Set
SREG(s)  1
Flag Clear
SREG(s)  0
Set Bit in I/O Register
I/O(A, b)  1
Clear Bit in I/O Register
I/O(A, b)  0
Bit Store from Register to T
T  Rr(b)
Bit load from T to Register
Rd(b)  T
Set Carry
C1
Clear Carry
C0
Set Negative Flag
N1
Clear Negative Flag
N0
Set Zero Flag
Z1
Clear Zero Flag
Z0
Global Interrupt Enable
I1
Flags
None
None
None
None
None
None
None
None
None
Z,C,N,V,H
Z,C,N,V
Z,C,N,V,H
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
None
None
T
None
C
C
N
N
Z
Z
I
#Clocks
-
1
1
1⁽¹⁾
2⁽¹⁾
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
XMEGA C3 [DATASHEET]
61
Atmel-8361F-AVR-ATxmega384C3-Datasheet–11/2014