AT32AP7002_1 Datasheet, PDF (763/896 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7002
34.12 Register Configuration Examples
34.12.1
STN LCD Example
This example is for an STN color (RGB) 320*240 display, 8-bit single scan, running at 70
frames/s with a LCDC Core Clock of 60 MHz. First, the pixel rate required to drive the display
should be determined by multiplying the total number of pixels on the display (320*240) by the
frame rate:
Pixel rate: (320*240 pixels/frame)*(70 frames/s) = 5,376,000 pixels/s
Next, the bit rate required to drive the display should be determined. Since the display is STN
color, each pixel consists of 3 bits (R,G,B), so the bit rate is just 3 times the pixel rate:
Bit rate: (5,376,000 pixels/s)*(3 bits/pixel) = 16,128,000 bits/s
Since the interface to the display is 8 bits wide, each PCLK cycle will transfer 8 bits to the display
(neglecting front porch and back porch PCLK cycles which do not transfer data). Thus, the
approximate PCLK frequency should be determined by dividing the bit rate by 8:
PCLK rate: (16,128,000 bits/s)/(8 bits/PCLKcycle) = 2,016,000 PCLKcycles/s = 2.016 MHz
Now that the desired PCLK rate is known, it is necessary to determine the value of the CLKVAL
field in LCD Control Register 1 (LDCCON1) and write to this register:
CLKVAL = ((60 MHz)/(2*2.016 MHz)) - 1 = 14 (rounded to nearest integer)
LDCCON1 = CLKVAL << 12;
Note that because CLKVAL had to be rounded to the nearest integer, the actual PCLK rate will
be (60 MHz)/((14+1)*2) = 2.000 MHz.
The next register that must be configured is LCD Control Register 2 (LDCCON2). This register
contains eleven fields which should be configured as follows:
DISTYPE = 1; // Display Type: STN Color
SCANMOD = 0; // Scan Mode: Single Scan
IFWIDTH = 1; //Interface Width: 8-bit
PIXELSIZE = 3; // Pixel size: 8 bits per pixel
INVVD = 0; // LCDD polarity: Normal
INVFRAME = 0; //Vsync polarity: Normal
INVLINE = 0; //Hsync polarity: Normal
INVCLK = 0; //PCLK polarity: Normal
INVDVAL = 0; //Dval polarity: Normal
CLKMOD = 0; //PCLK mode: PCLK only active during active display period for STN display
MEMOR = 2; // Memory Ordering Format: Little Endian
LCDCON2 can then be written as follows:
LDCCON2 = (MEMOR<<30) | (CLKMOD<<15) | (INVDVAL<<12) | (INVCLK<<11) | (INV-
LINE<<10) | (INVFRAME<<9) | (INVVD << 8) | (PIXELSIZE<<5) | (IFWIDTH<<3) |
(SCANMOD<<2) | (DISTYPE<<0);
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