AT32AP7002_1 Datasheet, PDF (533/896 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7002
write address must be chosen so that BA[1] or BA[0] are equal to one. See Section
28.8.1 for details about Extended Load Mode Register command.
10. The user must go into Normal Mode, writing the value 0 to the MR.MODE field and per-
forming a write access at any location in the SDRAM.
11. Write the refresh rate into the Refresh Timer Count field in the Refresh Timer Register
(TR.COUNT). The refresh rate is the delay between two successive refresh cycles. The
SDRAM device requires a refresh every 15.625µs or 7.81µs. With a 100MHz frequency,
the TR register must be written with the value 1562 (15.625 µs x 100 MHz) or 781 (7.81
µs x 100 MHz).
After initialization, the SDRAM devices are fully functional.
Figure 28-4. SDRAM Device Initialization Sequence
SDCKE
t_RP
SDCK
SDRAMC_A[9:0]
t_RC
t_MRD
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
DQM
Inputs Stable for
200 usec
Precharge All Banks _{1st Auto Refresh}
8th Auto Refresh
LMR Command ^{Valid Command}
28.7.2
SDRAM Controller Write Cycle
The SDRAMC allows burst access or single access. In both cases, the SDRAMC keeps track of
the active row in each bank, thus maximizing performance. To initiate a burst access, the
SDRAMC uses the transfer type signal provided by the master requesting the access. If the next
access is a sequential write access, writing to the SDRAM device is carried out. If the next
access is a write-sequential access, but the current access is to a boundary page, or if the next
access is in another row, then the SDRAMC generates a precharge command, activates the
new row and initiates a write command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge and active (t_RP) commands and between active
and write (t_RCD) commands. For definition of these timing parameters, refer to the Section
28.8.3. This is described in Figure 28-5 on page 534.
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